FVF-Based Low-Dropout Voltage Regulator with Fast Charging/Discharging Paths for Fast Line and Load Regulation

A new internally compensated low drop-out voltage regulator based on the cascoded flipped voltage follower is presented in this paper. Adaptive biasing current and fast charging/discharging paths have been added to rapidly charge and discharge the parasitic capacitance of the pass transistor gate, thus improving the transient response. The proposed regulator was designed with standard 65-nm CMOS technology. Measurements show load and line regulations of 433.80 μV/mA and 5.61 mV/V, respectively. Furthermore, the output voltage spikes are kept under 76 mV for 0.1 mA to 100 mA load variations and 0.9 V to 1.2 V line variations with rise and fall times of 1 μs. The total current consumption is 17.88 μA (for a 0.9 V supply voltage).Ministerio de Economía y Competitividad TEC2015-71072-C3-3-RConsejería de Economía, Innovación y Ciencia. Junta de Andalucía P12-TIC-186

LDO compensation with variable Miller series resistance

A new compensation method for low dropout (LDO) voltage regulators is proposed, where the series resistor of the conventional Miller compensation changes with the load current to track the variations in the first non‐dominant pole

Fully differential implementation of a delta-sigma modulator based on the pseudo-pseudo differential technique

Flicker noise and distortion are the main limitations in biomedical applications, especially for Switched Capacitor implementations, where the flicker noise is folded into the signal band. To remove the flicker noise and increase the linearity, the Pseudo-Pseudo Differential (P2D) technique has been proposed, where a single-ended signal is processed in a differential way. This paper presents the first silicon implementation of a second order Comparator-Based Switched-Capacitor (CBSC) delta-sigma modulator based on a variation of the P2D technique. Experimental results in a standard 180 nm CMOS technology show an improvement of 10 dB in the Peak SNDR, 5 dB in the DR, and 9 dB in the SFDR over its pseudo differential counterpart, which is the preferred differential implementation for CBSC circuits. Moreover, it is achieved with a reduction in the power consumption

Internally compensated LDO regulator based on the cascoded FVF

In this paper, an internally compensated low dropout (LDO) voltage regulator based on the Flipped Voltage Follower (FVF) is proposed. By means of capacitive coupling and dynamic biasing, the transient response to both load and line variations is enhanced. The proposed circuit has been designed and fabricated in a standard 0.5 mm CMOS technology. Experimental results show that the proposed circuit features a line and a load regulation of 132.04 mV/V and 153.53 mV/mA, respectively. Moreover, the output voltage spikes are kept under 150 mV for a 2 V-to-5 V supply variation and for 1 mA-to-100 mA load variation, both in 1 ms

Smart ICTs for the enhancement of traffic logistics in the Port of Seville

Las ponencias del congreso pueden descargarse desde: http://www.pianc.org.ar/_stage/papers_in.phpThis paper focuses in the optimization of intermodal transport by the development of a freight geolocation and telecontrol platform for intermodal transport. This system, Cooperative Unitized Tracking System (CUTS), is being developed under the project TECNOPORT2025, which is an initiative of the Port Authority of Seville (PAS), co-funded by the European Commission by means of the ERDF (European Region Development Funds), under the Pre-commercial Public Procurement model aiming the “Port of Future”

Smart Navigation System for the Port of Seville

Las ponencias del congreso pueden descargarse desde: http://www.pianc.org.ar/_stage/papers_in.phpThis paper focuses in the development of an information platform for rivers and integrated navigation aid system in waterways. The proposed system will not only offer vessel traffic services (VTS) and other RIS basic services but also those advanced and customized services of interest for the Port of Seville. This system, eRIO, is being developed under the project TECNOPORT2025 which is initiative of the Port Authority of Seville, co-funded by the European Commission by means of the European Region Development Funds, under the Pre-commercial Public Procurement model aiming the “Port of Future”

Adaptive Miller Compensation under Extreme Load Variations in IC-LDO regulators

A new frequency compensation technique for output buffers able to manage a wide range of loads, is proposed in this paper. To improve the stability, this technique implements a variable zero nulling resistor in a classical Miller compensation. A replica circuit senses the operating region of the output stage and generates the required value of the nulling resistor. In order to validate the effectiveness of the proposed technique, an Internally Compensated Low Dropout (IC-LDO) regulator based on a classical topology has been chosen and designed in a 65 nm standard CMOS technology. Results show that the proposed compensation scheme improves the Phase Margin of the IC- LDO regulator keeping it higher than 54o for load currents from 0 to 100mA at the cost of increasing only 10% the total quiescent power consumption and negligible area

A Compact Size Wideband RF-VGA Based on Second Generation Controlled Current Conveyors

This paper presents a methodology to design a wideband radio frequency variable gain amplifier (RF-VGA) in a low-cost SiGe BiCMOS 0.35 μm process. The circuit uses two Class A amplifiers based on second-generation controlled current conveyors (CCCII). The main feature of this circuit is the wideband input match along with a reduced NF (5.5–9.6 dB) and, to the authors’ knowledge, the lowest die footprint reported (62 × 44 μm2 area). The implementation of the RF-VGA based on CCCII allows a wideband input match without the need of passive elements. Due to the nature of the circuit, when the gain is increased, the power consumption is reduced. The architecture is suitable for designing wideband, low-power, and low-noise amplifiers. The proposed design achieves a tunable gain of 6.7–18 dB and a power consumption of 1.7 mA with a ±1.5 V DC supply. At maximum gain, the proposed RF-VGA covers from DC up to 1 GHz and can find application in software design radios (SDRs), the low frequency medical implant communication system (MICS) or industrial, scientific, and medical (ISM) bands.Ministerio de Ciencia, Innovación y Universidades de España RTI2018-099189-B-C22Agencia Canaria de Investigación, Innovación y Sociedad de la Información (ACIISI) del Gobierno de Canarias ProID2017010067 y TESIS201901010

IC-LDO Regulator with 600 nA Quiescent Current Using a Class AB Buffer

An ultra-low power Internally Compensated Low- Dropout (IC-LDO) regulator with a quiescent current consumption lower than 600 nA is proposed. It is based on the classical IC-LDO topology, which has been modified to include a class AB buffer between the output of the error amplifier and the gate of the pass transistor (MPASS). This way, a fast charge/discharge of its parasitic capacitance is achieved with the inherent low quiescent power consumption of class AB circuits. The proposed regulator has been fabricated in a standard 0.18- μm CMOS technology. Experimental results show that the proposed regulator has a Figure of Merit in the state of the art

Rail to Rail Fully Differential Track and Hold Based on Clocked Differential Difference Amplifier Using Resistive Local Common Mode Feedback

An efficient clocked class AB fully differential rail to rail differential difference amplifier is introduced. It is based on a two stage operational amplifier architecture with resistive local common mode feedback, floating gate transistors in the input stages and in the common mode feedback network. Its application in fully differential rail to rail high performance sample and hold circuits is discussed. Other applications discussed include fully differential buffers and single ended to fully differential converters with enable input. Experimental results of a test chip prototype fabricated in 0.5μm CMOS technology validate the proposed scheme. The fabricated track and hold has an SFDR=69.5dB with a clock frequency of 2MHz and 2Vpp, 200KHz input signals